Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation Accuracy

Efficient design of complex multiprocessor embedded systems requires fast technologies for early system cosimulation and evaluation. Host-compiled simulation has been proposed as an option for this purpose, since it enables accurately timed modeling at high simulation speeds. To achieve high accuracy, simulation technology has to consider internal details of the processing system, such as the modeling of processor pipelines or the estimation of cache misses. However, the modeling of these details must involve low overhead to ensure simulation speed. This paper proposes adding the modeling of the impact of a write buffer in write-through policies. The scheme presented is oriented to maximizing the accuracy vs. speed balance, proposing a static solution that results in no additional simulation overhead.