An FPGA-based all-digital transmitter with 9.6-GHz 2nd order time-interleaved delta-sigma modulation for 500-MHz bandwidth

An FPGA-based all-digital transmitter with 9.6-GHz 2nd order Time-Interleaved ΔΣ-modulation (TI-DSM) is presented. To improve the operation frequency of TI-DSM, bit separation architecture is proposed. This proposed architecture realizes the 1-bit digital transmitter with 500-MHz bandwidth. This is the widest bandwidth modulation among state-of-the-art FPGA-based all-digital transmitters.

I. Introduction

To cope with the recent demand of rapidly increased data traffic, 5G system requires wider bandwidth than 4G and 4G LTE advanced. It is said that at least 500-MHz bandwidth is required for representative 5G transceivers [1]. Accordingly, the increase of power consumption (especially, ADC (Analog to Digital Converter) and DAC (Digital to Analog Converter)) in transceivers becomes a big problem.