Research and implementation of reconfigurable architecture of DES and ZUC

Reconfigurable cipher chip has become a research hotspot because of its flexibility, security and good resource utilization. At present, research of reconfigurable cipher chip usually focuses on the same type of ciphers. In our paper, a reconfigurable architecture, which aims at block cipher algorithm DES and stream cipher algorithm ZUC, is proposed after reconfigurability analysis. This architecture unfolds DES into outer and inner pipeline, realizes the reconfiguration of S-box by using RAM-based look-up table and designs reconfigurable LFSR to achieve LFSR function of ZUC and pipeline data storage function of DES. According to the implementation results based on Altera's Stratix-V series FPGA, this reconfigurable architecture not only improves the security and flexibility of algorithms, but also saves the hardware resources.