Low power accuracy substitution circuit for image processing application

Power efficient is an important availability for various mobile devices and image processing applications. The proposed probabilistic adder is to trade a lesser amount of accuracy with reduced power dissipation. In this paper, the probabilistic adder is eliminating the some part of the carry propagation path in Least Significant Bit to reduce the power consumption and transistor count. The power consumption and probabilistic error behavior of the proposed adder is designed and compared with other adders. The low power probabilistic adders can save up to 60% power compared to conventional adders for a tolerable accuracy. When used in larger systems implementing image processing algorithms, power reserves of 40% are achievable.