A coupled thermal and mechanical modeling to investigate the stress of TSVs considering insulation layer

Through silicon via (TSV) technology has attracted much attention as a key method to realize chip stacking and interposers interconnected of 3D packaging. Due to the thermal load during fabrication and operation of TSV structure, the thermal stress will be produced owing to the structural material high CTE mismatch, which may lead to the failure of the TSV structure. In the case of uneven thermal load, the SiO
₂
with low thermal conductivity has a blocking effect on heat flow, thus it has a non-ignorable effect on thermal stress. In this paper, a planar TSV model of coupled thermal stress fields is established to demonstrate the influence of directional heat transfer. The influence of the thickness and structural parameters of SiO
₂
insulation layer on thermal stress is studied by finite element modeling. The simulation results show that larger SiO
₂
insulation thickness and smaller structural parameters q (q=D/P) can reduce the threat of thermal stress within the acceptable range. In addition, BCB and Parylene layer that replacing the SiO
₂
insulating layer can significantly reduce the thermal stress of the TSV structure. The average reduction is from 30% to 45% in majority region, and the reduction even reaches 70% at the Cu/SiO
₂
interface.