Area-Efficient Multihop Inductive Coupling Interface for 3D-Stacked Memory With 0.23-V Transmitter and Sub-10-μm Coil Design

An area-efficient low-power wireless inductive coupling interface for a 3-D-stacked high-bandwidth memory is presented. A test chip was fabricated in a 40-nm complementary metal-oxide semiconductor (CMOS) technology and 1.5-Gb/s 2.2-pJ/bit communication using a 0.23-V NMOS push-pull transmitter and 7-μm multilayer coils was experimentally confirmed. The low-voltage transmitter reduces power dissipation by 55% compared to the conventional one in measurement. The proposed 7-μm multilayer coils improve their mutual inductance by a factor of 4.5 compared to that of conventional single-layer ones. This letter discusses the multilayer coil wiring topology based on simulation and measurement. Optimization of the link budget achieves 7.1% power reduction compared to the conventional structure. Using this interface, a memory module consisting of eight 8-μm-thick memory dies and a base die in a 40-nm CMOS process and communicating at 3.6 Gb/s is extrapolated to achieve a 2.3-Tbps/mm
²
area efficiency and 6.1-pJ/bit energy efficiency. We also estimate that a 41-Tbps/mm
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0.1-pJ/bit memory interface is achievable in a 7-nm CMOS process.