A 0.9 pJ/b, Reference Clock Free, Delay-Based, All-Digital Coherent BPSK Demodulator

This letter proposes a novel reference clock free, delaybased coherent binary phase-shift keying (BPSK) demodulator suitable for biomedical devices which receive power and data through the same wireless link. The proposed BPSK demodulator mixes the BPSK input signal and its copy delayed by a half of the carrier period to generate a data Hipping signal whose rising edges indicate when the phases of the BPSK signal Hip. The data are then recovered by sampling the BPSK input signal using the derived data Hipping signal. A phase selector recovers the coherent clock with a 50% duty cycle by selecting either the delayed BPSK input or its complement according to the recovered data. The open-loop operation of the proposed BPSK demodulator enables it to achieve a data rate as high as the carrier frequency. The all-digital implementation makes the demodulator compact, low power, and able to operate at 0.5 V. A test chip running with a 13.56-MHz carrier has been designed and fabricated. Measurement results show that at 0.9 V and a data rate of 13.56 Mb/s, the proposed demodulator only consumes 12.2 μW, corresponding to an FoM of 0.90 pJ/b. This FoM is at least 61 times better than those of the state-of-the-art designs.