A Sub-mW On-Chip Period-Jitter Measurement Circuit Using Automatic Hidden Runtime Resolution Calibration

It is challenging to design an on-chip jitter measurement circuit (OCJM) for complex systems-on-chip (SoCs) with high resolution at low power that is resilient to PVT variations. In this work, an approximate period-to-digital converter (APDC) and a parameter-extraction and resolution-calibration circuit (PERC) are proposed for use in an OCJM to achieve the design goals of high resolution without a reference clock and automatic hidden runtime resolution calibration for high PVT-variation resilience. The measurement results of a 28-nm test chip show that a 1.0-ps resolution specification can definitely be met at different PVT corners during runtime. The measurement results from 15 chips show that the OCJM is resilient to chip-to-chip variations. The proposed OCJM consumes 0.95 mW, which corresponds to 8% of the power consumption in a state-of-the-art stochastic time-to-digital-based OCJM reimplemented with the same CMOS technology.