A High-Output Power 1-V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology

A flexible, low-cost design solution for in-field-programmable (IFP) metal eFuse is reported. The design maximizes fuse yield through a tunable program voltage provided by a two-stage charge pump (CP), placed in closed loop (CL) with a low dropout regulator (LDO). The integration of CP and LDO solves electrical over-stress (EOS) concerns and achieves stability and low voltage operation through several design innovations. The CP integrates with the fuse macro by distributed, extra-high voltage (EHV) power-gate power-switch (PGPS), which switches between CP and nominal supply for fuse read, increases array efficiency, and reduces leakage. The solution does not require a specific power sequence or metal–insulator–metal cap, enabling maximum design adaptability and integration flexibility. This design is implemented and characterized on Intel 4 technology, where >99.9% successful fuse bit program was measured across [−40 °C, 125 °C] temperature, and down to 0.95 V.

I. Introduction

One-time programmable (OTP) metal fuse is an on-chip memory, programmed during both high-volume manufacturing (HVM) and in the field to enable features, such as chip identification, post-Si circuit tuning, security key storage, etc. Metal fuse requires an extra-high voltage (EHV) voltage (~1.6–2.1 V) and 10 s of mA to properly program. In an HVM setting, a high-quality HVM supply provides a specific, yield-optimized programming voltage. On the customer platform, this function is performed by an in-field-programmable (IFP) power solution. Prior IFP solutions use either an on-die power switch with generic EHV platform supply, or an on-die power generation, such as charge pump (CP) or low dropout regulator (LDO) [1], [2]. The power switch with platform supply typically creates a power sequence requirement between nominal and EHV supplies to avoid electrical over (EOS) and prevents the technology from choosing a yield-optimized programming voltage since this supply is shared with nonfuse IP. Prior on-die implementations used either a single-stage open-loop (OL) CP, which provides lower voltage head room for yield optimization for different processes or rely on thick-gate (TG) devices, which are incompatible with performance-optimized logic process [1], [2]. The proposed solution adds another stage to the single-stage CP and places it in a feedback loop for tunability, and to mitigate EOS from the added stage. An internal resistor reference is used, and bandgap reference is also included where greater PSRR might be required. The CP connects to the fuse macro via power-gate power-switch (PGPS), which switches between CP output and nominal voltage for read. Fig. 1 shows the system diagram, including CP with feedback, BGref, and fuse array with PGPS, with fanout to multiple arrays. Fig. 1.

CL CP, BGref, and fuse memory with PGPS.