I. Introduction
Time interleaving technique has been widely used in analog electronics to achieve high speed signal processing [1]. In essence, the technique is a parallel array signal process where individual array elements operate with a suboptimal speed and outputs from the array elements are interleaved parallel in time. In such ways, effectively overall signal processing speed can be increased by the factor of time interleaving factor. In fact, the parallelism in signal processing has been a successful tradeoff of a system complexity for a high sampling speed under a limitation of transistor speed in data converter designs [2]. This paper proposes the time-interleaved parallel signal processing in phased arrays to enable integrated phased array transceivers toward sub-terahertz regimes under a constraint of active device speed limitation.