The systematic design for high speed interpolated/averaging ADC

A systematic design methodology, composed of a BW/gain model and an offset modeling mechanism, is proposed for high-speed interpolation/averaging ADCs. The methodology is able to conduct a systematic analysis and reaches an optimized ADC design with given specs (i.e., resolution, speed, input range, power, input CM, etc.). It shows significant advantage over the traditional trial-and-error ADC design approach with respect to performance, design efficiency and reliability in nano-meter technologies. Using our methodology, a 4-bit 5GSps prototype ADC is designed and fabricated in a 65nm CMOS technology. The measurement results show that our ADC has indeed achieved an outstanding overall performance compared to the reported state-of-the art ADCs.