A low-jitter PLL with new cross-coupled VCO delay cell for SerDes CDR in 55-nm CMOS technology

This paper presents a 1.2-V low-jitter PLL which provides 3.125-GHz eight-phase clocks for the SerDes CDR with the data rate of 12.5-Gb/s. The PLL circuit incorporates a ring VCO, a precise CP and a dynamic PFD. A fourth order ring VCO with the gain KVCO of 1-GHz/V is designed in order to generate low-jitter eight-phase clocks, while a new delay cell without the tail current source is proposed. Moreover, a dynamic PFD circuit is designed to meet the demand of the speed. A precise CP based on the current mirror is used to change the phase error detected by the PFD into the current signal. Realized in 55-nm CMOS technology, the PLL can provide rail-to-rail eight-phase clock, with the frequency of 3.125-GHz and the jitter less than 1.88ps.