I. Introduction
One of the most fundamental issues in VLSI design is power dissipation. With the continuously enhancing chip's complexity and amount of transistors on a chip, circuit's power consumption is rising as well. Most of the VLSI applications require memory for storing the information. So the power consumption in the memory cells should be reduced to have the better battery life for the devices. Hence research on low power techniques to make the products highly energy efficient, the design of the memory cell optimized for low power applications is required. Various researchers have proposed a number of techniques for power reduction like charge recycling [1] [9], shared bitline architecture [6], 9- T cell [4] and standby leakage reduction [5] [10] etc. In this paper, power gating techniques is used to reduce the standby power for the memory cells. For the reduction of the active power, charge recycling technique is used for the read as well as write operation. So basic aim of the work presented in this paper is to reduce the power dissipation in the 64 bit SRAM memory array both for the active power as well as for the standby power. The 6T cell is as shown in the following figure 1. It is the most common industry standard used for the organization of the SRAM. It is having two PMOS and 4 NMOS transistors. In this structure the two inverters are used in the cross coupled configuration. During the write operation of the transistor logic’ 1’ is provided to the word line and place the data to be written on the bit lines. Similarly during the read operation the word line is kept high, but the bit lines are precharged to VDD/2. So one sourcing and one sinking current will flow through the bit lines, which is sense by the sense amplifier. And the corresponding output is produced at the output of the sense amplifier.
6-t SRAM cell