High-level test data generation for software-based self-test in microprocessors

A new high-level fault model and test generation method for software-based self-test in microprocessors (MP) is proposed and investigated. The model is derived directly from the instruction set of the given MP. A deterministic high-level method and algorithm for test data generation based on this fault model are proposed for the control part of MP. For the data path of MP, pseudo-exhaustive test generation method is proposed, which provides high gate-level SAF coverage. The methods proposed are fully high-level approaches, and no gate-level ATPG is needed. The capability of the new approach to achieving high gate-level fault coverage is demonstrated by low-level SAF simulation.