A new 16-bit high speed and variable stage carry skip adder

Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage size and variable stage size. In this paper, fixed stage and variable stage carry skip adder configurations have been analyzed and then a new 16-bit high speed variable stage carry skip adder is proposed by modifying the existing structure. The proposed adder has seven stages where first and last stage are of 1 bit each, it keeps increasing steadily till the middle stage which is the bulkiest and hence is the nucleus stage. The delay and power consumption in the proposed adder is reduced by 61.75% and 8% respectively. The proposed adder is implemented and simulated using 90 nm CMOS technology in Cadence Virtuoso. It is pertinent to mention that the delay improvement in the proposed adder has been achieved without increase in any power consumption and circuit complexity. The adder proposed in this work is suitable for high speed and low power VLSI based arithmetic circuits.