A 10-bit 150MS/S SAR ADC with a novel capacitor switching scheme

This paper presents a 10-bit 150-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC). Firstly, combining the merged capacitor switching scheme (MCS scheme) with the split capacitive digital-to-analog converter (split CDAC), a novel capacitor switching scheme is presented which greatly improve the power efficiency of the ADC. Moreover, the use of a non-binary redundancy algorithm corrects the incomplete settling of the CDAC and increases the sample rate of the ADC. The ADC achieves an SNDR of 51.5 dB for a 15 MHz input and 49.6 dB for a 74.5 MHz input, and the total power consumption is 537 μW from a 1.2-V supply.