Design of subthreshold adiabatic logic based combinational and sequential circuits

Power dissipation in VLSI circuits has become increasingly important for modern portable devices. Adiabatic is a novel energy conserving logic for ultra low power circuits. Adiabatic logic is energy efficient and less logic overhead. Fully adiabatic and partial energy recovery adiabatic circuits are two major logics which work for wide range of frequency. Subthreshold adiabatic logic is a novel approach for low energy consumption and low speed digital circuits which work for low frequency. In this paper one combinational and sequential circuit is designed using static CMOS and SAL using CADENCE 45nm technology. Power results show energy saving in SAL compare with static CMOS.