OpenSMART: Single-cycle multi-hop NoC generator in BSV and Chisel

The chip industry faces two key challenges today - the impending end of Moore's Law and the rising costs of chip design and verification (millions of dollars today). Heterogeneous IPs - cores and domain-specific accelerators - are a promising answer to the first challenge, enabling performance and energy benefits no longer provided by technology scaling. IP-reuse with plug-and-play designs can help with the second challenge, amortizing NRE costs tremendously. A key requirement in a heterogeneous IP-based plug-and-play SoC environment is an interconnection fabric to connect these IPs together. This fabric needs to be scalable - low latency, low energy and low area - and yet be flexible/parametrizable for use across designs. The key scalability challenge in any Network-on-Chip (NoC) today is that the latency increases proportional to the number of hops. In this work, we present a NoC generator called OpenSMART, which generates low-latency NoCs based on SMART1. SMART is a recently proposed NoC microarchitecture that enables multihop on-chip traversals within a single cycle, removing the dependence of latency on hops. SMART leverages wire delay of the underlying repeated wires, and augments each router with the ability to request and setup bypass paths. OpenSMART takes SMART from a NoC optimization to a design methodology for SoCs, enabling users to generate verified RTL for a class of userspecified network configurations, such as network size, topology, routing algorithm, number of VCs/buffers, router pipeline stages, and so on. OpenSMART also provides the ability to generate any heterogeneous topology with low and high-radix routers and optimized single-stage pipelines, leveraging fast logic delays in technology nodes today. OpenSMART v1.0 comes with both Bluespec System Verilog and Chisel implementations, and this paper also presents a case study of our experiences with both languages. OpenSMART is available for download2 and is going to be a key addition to the emerging open-source hardware movement, providing a glue for interconnecting existing and emerging IPs.

I. Introduction

Networks-on-Chip (NoC) is a key component of almost all chips today. The domains vary from (i) many-core chips in HPC supercomputers and high-end servers with tens to hundreds of homogeneous cores [1]–[3], to (ii) mobile and embedded SoCs with tens of heterogeneous cores and controllers [4], [5], to (iii) GPUs with hundreds of SMs [6], to (iv) domain-specific accelerators, such as machine learning, with hundreds of processing elements [7], [8]. Without loss of generality, we refer to end point cores, accelerators, PEs, caches, etc. as “IPs” in this work. NoC is the interconnect backbone connecting IPs communicating each other and a critical IP block itself for plug-and-play designs. As the number of IPs in a hardware system increases, the communication fabric also needs to scale so that it does not become a performance or energy bottleneck.