Low-power optimisation of a pixel array architecture for next generation High Energy Physics detectors

A large scale pixel readout chip is being designed by the RD53 Collaboration, in order to prove the suitability of 65 nm technology for the extreme operating conditions foreseen for the High Luminosity upgrades of the ATLAS and CMS experiments at CERN. The use of advanced digital design and simulation tools is essential to guide architectural and implementation choices for the design and optimisation of pixel chips which will be powered from a serial powering scheme. In this work, low power design techniques are reviewed and critically selected based on the requirements of the target application. Chosen techniques are adopted and results of the low power optimisation are presented for a basic unit of the system.