A 0.05–6 GHz voltage-mode harmonic rejection mixer with up to 30 dBm in-band IIP3 and 35 dBc HRR in 32 nm SOI CMOS

This paper presents a new harmonic rejection mixer (HRM) circuit that uses resistive scaling to achieve very high linearity and a harmonic rejection ratio (HRR) greater than 35 dBc. The mixer employs 4 double-balanced mixers driven by 8 LO phases with 12.5% duty cycle to isolate different paths. The mixer switches have been implemented with thin- and thick-oxide transistors to improve linearity further at the cost of reduced tuning range. The measured conversion loss at an IF of 100 MHz is 6.6-10.8 dB and 6.4-9.2 dB for an RF of 0.05-6 GHz and 0.05-4 GHz, and the measured in-band IIP3 is 23-19 dBm and 31-21 dBm. The power consumption is 29-126 and 98-298 mW for the thin-oxide and thick-oxide designs, respectively. To our knowledge, this is the highest linearity and widest tuning range reported to-date for a harmonic rejection mixer. Application areas are in high-linearity wideband receivers, and in base-station and instrumentation receivers with reduced front-end filtering requirements.