FPGA design and verification for lossless ECG coding compression

This paper presents a lossless, low latency, low power dissipation compression for long-term wearable ECG monitor to reduce the amount of data, avoiding costly unnecessary wireless data transmission to extend battery life. In this research, we introduce an approach base on run-length coding, which compresses ECG signal by preforming duplicate data encoding by using the characteristics of ECG signal distribution and the correlation among adjacent heartbeats and achieve lossless compression effect. In the hardware development environment, the design has been verified by using FPGA and tested by MIT/BIH ECG database. The experimental results of the algorithm are correct and close to the software simulations.