Isolation integrity of drain/gate contact exposed with source/drain extension length for SOI p-channel FinFETs

This work demonstrates the isolation integrity between gate contact and source or drain contact with the variety of source/drain extension lengths. The trend of isolation capability not only linearly followed the extension length, but related to the formation of liner spacer. As the channel width (W
_fin
=0.11μm) was fixed, the I
_GD
leakage at channel lengths L
_g
= 0.24, 0.16, and 10μm with L
_SDE
= 160nm is larger as V
_G
= -Vcc. However, the I
_GD
value with L
_SDE
= 60nm is larger, located at L
_g
= 0.24, 0.12, and 0.5μm as the same voltage bias.