3D-IC technology and reliability challenges

Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in the paper. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully. As for reliabilities of 3D-IC s with TSVs, however, several issues still remain prior to volume productions. In general, there are millions of TSVs and metal microbumps in vertically stacked thinned Si chips. Therefore, electrical characteristics of 3D-ICs are affected by such structures. The paper shows reliability issues in 3D-IC with TSVs. Both TSVs and metal microbumps cause local mechanical stress and strain in stacked thinned Si chips due to coefficient of thermal expansion (CTE) mismatch between Si and Cu TSV and metal microbump. As the thickness of Si chip has to be reduced less than several tens of μm, this might cause residual stress and crystal defects in the thinned Si chip. In addition, both intrinsic and extrinsic gettering layers to suppress metal contaminations and crystal defects might be eliminated from the Si chip by thinning process. This paper focuses on the most potent reliability issues such as Cu contamination and thermomechanical stress, and discusses new evaluation methods for the issues.