Introduction
Modeling and yield prediction of the semiconductor product has been an integral part of the IC manufacturing process from the very early stages of the industry. For accuracy, the detection and measurement of the yield detractors must be precise. The capability to image and measure yield detractors before the completion of the lengthy serial process flow to manufacture a product has be a key tool for successful technology development and the effective monitor and control of the mass production process. However, as key features and dimensions continue to shrink, the layout environments need to be better reflected in the electrical test structures used to breakdown, measure, and determine the root cause of parametric and systematic pattern defects.