Assessing device reliability margin in scaled CMOS technologies using ring oscillator circuits

Device performance enhancement elements are frequently reducing device reliability margin in scaled CMOS technologies. To assess the impact of HCI degradation on digital CMOS logic we study the frequency degradation (Δf/f) of ring oscillator circuits using core and IO devices in 14nm FinFET technology and correlate the results with discrete device degradation using the conventional DC and a novel AC HCI stress methodology. While for IO devices the traditional scaling factor of 50x used to define DC equivalent HCI targets is applicable, additional HCI margin is demonstrated for core devices bringing relief for device optimization in scaled technology nodes.