Extreme Learning Machine Optimization Based High Speed Parallel Algorithm for Reed-Solomon Decoding

A lot of research has been done on efficient implementation of RS code encoders and decoders as VLSI chips. However, none of them tries to seek a unified approach for solution to obtain VLSI hardware for RS encoders and decoders which can be easily configured for use across a large set of application areas with varying specifications. In this paper, a novel parallel RS decoding algorithm suitable for multi-Gb/s communication systems has been designed. Extreme Learning Machine is used in order to overcome the drawbacks of existing designs. Through the proposed design the performance benefit of the algorithm is truly witnessed. It is suitable for high speed real-time systems with hard timing constraints. The design is implemented and simulated in Xilinx Virtex 6 FPGA through MATLAB and VHDL.