Image segmentation implementation based on FPGA and SVM

In this paper a hardware implementation architecture for image segmentation based on FPGA and SVM is proposed. Compared with the existing hardware parallel computing method, the proposed architecture can establish work mode of serial computing and parallel transmission by advantage of least squares support vector machines (LS-SVM) and parallelism of recursive neural network. With increase of amount of samples, consumption of hardware resources is not obvious, and computation speed is still at a high level. In this paper, theoretical simulation of LS-SVM algorithm is realized and finally the hardware description language Verilog HDL is used to implement theoretical algorithm on FPGA hardware. Experimental results show that the proposed hardware architecture of image segmentation algorithm based on FPGA and SVM is practical and effective in image segmentation.