Modeling of embedded non-volatile memories using Array Emulation for Full Chip spice and mixed mode design verification of complex automotive SOCs

Application code and data size have increased manifold in designs created these days, increasing the usage of embedded non-volatile memory (NVM) inside Automotive SOCs. Embedded NVM provides better security, SOC specific customization, and better integration to other SOC components. It also interacts with many critical modules, like Power Management Controller (PMC), Reset-sequencing State control machine, etc.; while also playing a very important role in power-up sequencing and mode transitions of the chip, since it contains the analog trimming, firmware and final customer application code. The NVM is a big complex component containing Digital and Analog sections, along with Bitcell Arrays and multiplexers. Once integrated in a SOC, it is quite important to check proper functioning of SOC and NVM across power-up and low-power-mode transitions. At present, NVM verification at IP level is done in parts, with individual sub-modules tested separately and limited verification of complete NVM IP after its sub-modules modules are stitched together. At SOC level, verification is done using behavioral model of NVM, which again loses electrical aspect of the signals. Thus mixed-mode simulations at SOC-level are needed for NVM. But, taking the entire NVM-Array in SPICE is an un-necessary load of millions of MOSFETs on the simulator, and beyond the capacity of many tools. The repeated memory-bank-structures do contain a lot of analog circuitry, and optimized techniques can allow for a simulation friendly design-size. We have developed method to model the NVM which allow us to run Chip-level simulations with a SPICE & Verilog-A/AMS views of the NVM. In this paper, we describe these modeling methods and the advantages of the additional coverage obtained.