PBTI and PBTS testing of 0.25 μm pMOSFET devices for analog circuits

Parametric device shifts occur in a 0.25 μm CMOS sense amp circuit during a High Temperature Operation Life (HTOL) test, due to the positive bias stress on the pMOSFET devices. The positive gate bias from the HTOL stress causes a larger negative shift in the threshold voltage of the 5V pMOSFET devices and a mismatch in the transconductance of the differential pair, resulting in a decrease in the gain of the amplifier. Negative shifts in threshold voltage are also observed for 5V pMOSFET test structures for devices with no protect diodes (antenna ratio = 1000:1) after either Positive Bias Temperature Instability (PBTI) tests or Positive Bias Temperature Stress (PBTS). The PBTI and PBTS are caused by positive charge from interface states and bulk oxide traps.