The physical explanation of TDDB power law lifetime model through oxygen vacancy trap investigations in HKMG NMOS FinFET devices

In this paper, the physical explanation of the time dependent dielectric breakdown (TDDB) power law lifetime model is successfully interpreted through the analysis of oxide trap generation in HK/IL gate stack in NMOS-FinFET technology. The experiments are performed using the stress induced leakage current (SILC) spectrum methodology. It is found that the TDDB power law model has a strong correlation to deep trap generation. Shallow traps, on the other hand, play a role in the increase of SILC behavior and also promote further deep trap formation during the gate oxide degradation. In addition, temperature dependent and recovery voltage dependent TTDB studies reveal that, the deep trap generation is responsible for the permanent damage and the formation of percolation path during the gate oxide degradation. Through the oxygen trap study, the physics of TDDB power law lifetime model can be successfully explained.