Automatic technology migration of analog IC designs using generic cell libraries

This paper addresses the problem of automatic technology migration of analog IC designs. The proposed method introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit classes. In addition to technology independence, reusing the testbenches when adding new topologies for the already implemented circuit classes also improves design productivity. The new method is implemented and tested using a state-of-the-art multi-objective multi-constraint circuit-level optimization tool for circuit sizing, and is validated for the design and optimization of continuous-time comparators, including technology migration between two different design nodes, respectively, XFAB 350 nm technology and ATMEL 150 nm SOI technology.