Design of an efficient multiplier using Vedic mathematics and reversible logic

Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. This paper presents the new design of 2×2 Urdhva Tiryakbhayam multiplier using reversible logic gates. The proposed 2×2 Reversible Vedic multiplier has better design constraints than previous existing design.