Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits

Spin Transfer Torque (STT) is a promising technology for storage in which the information is stored in the form of magnetic orientation of a Magnetic Tunnel Junction (MTJ) rather than electric charge. Besides memory applications, this technology is promising for non-volatile reconfigurable logic design. The major challenge in realizing this technology is the power and performance overhead associated with reading the state of MTJs (high and low resistance states) and converting it into high and low voltages for interface to next stage circuits. In this paper, methods are proposed to reduce this overhead by MTJ resistance optimization at the device level and mapping multiple low fan-in logic gates into a STT-based Look Up Table (STT-LUT) at the circuit level. The paper demonstrates that by optimally mapping logic gates to STT-LUTs, the power and performance overhead of a reconfigurable design can be reduced to become competitive with a full-custom design. Our results on an arithmetic benchmark circuit shows that by optimal logic gate mapping into STT-LUTs, the power and performance of the design is improved by 65% and 54%, respectively, compared to the design where each individual logic gates is replaced by an STT-LUT.