Hardware implementation of Hierarchical Temporal Memory algorithm

In this paper, a hardware ASIC implementation of the Numenta Hierarchical Temporal Memory (HTM) algorithm is presented. Each column in the neural network is implemented as a processing element (PE). Neuron cells in columns are built as identical cell modules. Dedicated register files for each module cell are employed to replace the conventional centralized memory organization. A complete neural network is built as a matrix of PEs connected in the mesh network. Both first order and high order network are successfully performed on a 20×20 PE matrix using images from MNIST dataset as input patterns. The power and area of a single PE including 2 cell modules are 1.29 mW and 17511 μm
²
respectively. The average processing time in the proposed implementation is 4.52 μs in learning mode and 4.39 μs in inference mode. Compared to the performance of a software implementation on the 4 threads CPU, the ASIC version provides a 329.6× speedup in learning mode.