DC Drain Current Model for Tunnel FETs Considering Source and Drain Depletion Regions

This paper presents a 2-D model for the DC drain current of a tunnelling field-effect transistor (TFET) considering the source and the drain depletion regions. Analytical expressions are derived for the surface potential, electric field and the band to band generation rate. The drain current is obtained by numerically integrating the generation rate across the entire device. The model is able to predict the ambipolar current as well as the effects of drain voltage in the saturation region. The model uses a semi-empirical approach to capture the transition between the linear and the saturation regions, which gives an infinitely differentiable transfer characteristics. This model includes the effects of drain voltage, gate metal work function, oxide thickness, and silicon film thickness. The accuracy of the model is confirmed by a comparison with 2-D numerical simulations. It is also demonstrated that the proposed model is scalable down to a channel length of 20 nm.

I. Introduction

With the reduction of CMOS device dimensions to the sub-100 nm range, the interest in low power applications has increased. However, problems such as high OFF-state currents, drain induced barrier lowering (DIBL), high subthreshold slope (SS) and other short channel effects (SCEs) limit the applicability of a conventional MOSFET in the low power regime. To address some of these problems, the tunnel field effect transistor (TFET) has been proposed as an attractive alternative, and has been extensively studied [1]–[9].