DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency

A major challenge for the widespread adoption of phase change memory (PCM) as main memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation (i.e., an operation that writes '1') is 2-5 times longer than the latency of a RESET operation (i.e., an operation that writes '0'). For this reason, the average write latency of a PCM system is limited by the high-latency SET operations. This paper presents a novel PCM architecture called DyPhase, which uses partial-SET operations instead of the conventional SET operations to introduce a symmetry in write latency, thereby increasing write performance and throughput. However, use of partial-SET decreases data retention time. As a remedy to this problem, DyPhase employs novel distributed refresh operations in PCM that leverage the available power budget to periodically rewrite the stored data with minimal performance overhead. Experiments with PARSEC benchmarks indicate that our DyPhase architecture achieves 16.2% less average latency and 27.6% less EDP on average over other PCM architectures from prior works.

I. Introduction

For decades since its emergence, dynamic random access memory (DRAM) has supported the demands on main memory capacity and performance [1]–[5]. In the “big data” era, the next generation memory systems must be capable of offering the memory capacity required to maintain large data structures [1]. However, scaling DRAM below 22nm to increase capacity is currently unknown [2], and at 22nm, DRAM dissipates a large amount of leakage power [3]. These limitations make DRAM less suitable for next generation main memory in the “big data” era.