A fast and simple routing algorithm for butterfly architecture

This paper presents the challenges we met during the development of simulators for NOC architectures. This paper focuses on the simulation of Buttery architecture. In earlier bus architectures when the size increases the communication between different nodes became a difficult task. The bus was a broadest module. It contains lots of lines. Its number is increasing. Some module is capturing this lines, transmitting electronic information and releasing into bus for somebody else to use. This bus based architectures of SoC could not solve many applications due to timing problem and so on. This is why we introduced the new paradigm of NoC. Basically this idea is to take this more less articulate and transform it into a very elegant kind of communication mean which we borrow from networking, i.e. routing short lines and we are putting routers in between. The future of VLSI is based on the NoC based architectures. To measure the performance simulation is inevitable. Thus we present this paper on the challenges we faced during the development of a simulator for buttery architecture.