SSTL based thermal and power efficient RAM design on 28nm FPGA for spacecraft

In this paper, an approach is made to design a Thermal and Power efficient RAM for that reason we have used DDR4L memory and six different members of SSTL I/Os standards on 28nm technology. Every spacecraft requires most energy efficient electronic system and for that very purpose we have designed the most energy efficient RAM. In this design, we have taken two main parameters for analysis that is frequency (1600 MHz) and Voltage (1.05V). DDR4L operates at the lowest Voltage compared to available RAM's. Environment (LFM, Heat Sink, and Capacitance) is kept constant. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. We have done our analysis with different I/O standards for DDR4L RAM. When we scale down from 288.15K to 348.15K there is maximum total power reduction in SSTL135_R as compared to all considered I/O standards. When we compared different members of SSTL for different temperatures and I/O power we observed maximum thermal efficiency in SSTL135_R at minimum and maximum temperature as compared to all other considered I/O standards. When we scale down from 348.15K to 288.15K there is no power reduction in Clock power, Logic power, Signal power, BRAMs and I/Os power respectively.