Power integrity analysis for solid state drive PCB

Today in high-speed digital design, system-level Power Integrity (PI) analysis has become inevitable due to ever increasing data rates for both serial I/O interface and memory interface. The present trend in high-speed digital circuits is increasing speed and density, thereby consuming more current and operating at lower supply voltages. The increase in switching speed and total current consumption combined with lower supply voltages has decreased the noise margin making the components more susceptible to power supply noise. The objective of Power integrity analysis is to provide a stable DC voltage within the specified voltage ripple limits across the frequencies of interest. In this paper post layout power integrity simulation for Solid State Drive PCB using Mentor Graphics Hyperlynx PI simulation tool is discussed.