19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter

Digital-PLL frequency synthesizers for wireless applications have become popular in the sub-10GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the integer-N type [1]. This is due to limited DCO tuning resolution and challenges in phase digitization including limited resolution, linearity, and input frequency of the TDC. The 60GHz ADPLL in [2] uses a 32× CML/injection-locked-frequency-divider chain in the DCO-TDC interface, which results in high power consumption (>0.5 of total power), large area, and high in-band phase noise. This paper presents a 60GHz phase-domain ADPLL with a 16GHz tuning range, digital phase extraction at f
_DCO
/4, and several on-chip calibration techniques that enable low in-band phase noise and spurs.