A novel high-speed divide-by-3/4 prescaler

A novel extended true single-phase clock-based (ETSPC) divide-by-3/4 prescaler is presented. Instead of the conventional technologies (i.e. transmission gates, logic gates), by using the pass transistor logic circuit, only two transistor are needed to realized the mode selection control. The operation speed is improved by reduction of the critical path delay between the ETSCP flip-flops. Since the number of additional transistors compared with the counter for divider is only two, the low power consumption can be achieved. Simulation results in a standard 180nm CMOS process show that the operation speed of the proposed divide-by-3/4 prescaler is 15.9%∼103% faster than the conventional divide-by-3/4 prescaler.