QR decomposition using FPGAs

This paper describes the architecture and implementation of a high performance QR decomposition IEEE754 single precision floating point core, using a modified Gram-Schmidt algorithm. Using Intel's new floating point Arria 10 FPGAs, synthesis is used to generate column high functional units, giving O(n
²
) processing times. The modified Gram-Schmidt algorithm is expressed in a different order to combine the elements of the column calculations at a later stage, which reduces the data dependencies in a deeply pipelined hardware implementation. Special vector structures in the tools and hardware architecture are supported to maximize performance. The matrix sizes are parameterized, with both square and rectangular complex matrixes supported. Two versions of the QRD core, using an example matrix size of 50×100 are presented, one of a conventional FPGA architecture (Stratix V) and the other on Floating Point FPGA (Arria 10) with comparative data on logic, registers, DSP, memory resources and Fmax. Matrix throughput and GFLOPS/W results are also provided. In addition, results for specific matrix sizes common in wireless MIMO processing are also presented.