Routing perturbation for enhanced security in split manufacturing

Split manufacturing can mitigate security vulnerabilities at untrusted foundries by exposing only partial designs. Even so, attackers can make educated guess according to design conventions and thereby recover entire chip designs. In this work, a routing perturbation-based defense method is proposed such that such attacks become very difficult while wirelength/timing overhead is restricted to be very small. Experimental results on benchmark circuits confirm the effectiveness of the proposed techniques. The new techniques also significantly outperform the latest previous work.

I. Introduction

Maintaining a state-of-art semiconductor manufacturing facility has become expensive; the cost of owning and maintaining a foundry costs several billion dollars [1]. Thus, only high-end commercial foundries manufacture high performance, mixed-system integrated circuits (ICs), especially at the advanced technology nodes [2]. Many design companies cannot afford owning and acquiring expensive foundries; hence, they outsource their fabrication process to these “one-stop-shop” foundries. While globalization of IC production flow has reduced design complexity and fabrication cost, it has introduced several security vulnerabilities [3]. An attacker anywhere in the IC supply chain can perform the following attacking techniques: reverse engineering, malicious circuit insertion, counterfeiting, and intellectual property (IP) piracy [2], [4]–[7]. Because of these attacks, the semiconductor industry loses billions of dollars annually [8]. These attacks are possible because designers have no control over their design in this distributed supply chain. More importantly, current electronic design automation (EDA) tools do not consider security as a design objective.