A 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components

This paper presents a prototype of 14bit 80kSPS non-binary cyclic ADC without high accuracy analog components and complicated digital calibration. Since the redantancy of non-binary ADC tolerates the non-idealities such as capacitor mismatch and finite amplifier gain, the design consideration of this high accuracy ADC are be focused on the capacitance of sampling capacitor to satisfy the overall kT/C noise target, the drivability and linearity of amplifier. The proposed proof-of-concept cyclic ADC is designed and fabricated in TSMC 90nm CMOS technology. Peak SNDR×81.9dB is achieved while Fs×80kSPS with a poor gain of the amplifier as low as 66dB dissipating 8mW at VDD×3.3V in analog circuits.