Area and Throughput Analysis of Different AES Architectures for FPGA Implementations

Advanced Encryption Standard is used to cipher data with the motive of secure transmission over a communication channel. In this paper some architectures for AES-128 implementation have been discussed. The basic AES core has been developed for encryption and decryption using Look-up Table and Composite Field Arithmetic. It describes the basic structure of AES in Electronic Codebook mode working on 128 bits of data undergoing ten rounds of processing to produce 128-bits of cipher text. Outer pipeline is applied to the implementation of Encryption and Decryption. Further different stages of the inner pipeline are applied to the same encryption structure and compared in terms of throughput and area. Wide rangeof throughput is observed with different area requirements. The implementation results are compared among different designs and with other reference papers. All these implementations are synthesized, mapped, placed, routed and simulated using Xilinx 9.2 on Spartan and Virtex series of devices.