VHDL code generation as State Machine from a Data Flow Graph

Operation scheduling is a fundamental problem in mapping an application to electronic devices. In scenarios where these schedules are made on Data Flow Graph (DFG), it is necessary to convert the result to Hardware Description Language (HDL) code. We present a detailed approach for generate VHDL code described in a Data Flow Graph (DFG). We generate VHDL code corresponding to Moore Finite State Machine (FSM), because is similar with the logic of the DFG. We use 20 DFGs from benchmark Mediabench to compute different experiments and we report the occupied area (Slice registers and LUTs) of VHDL codes on a FPGA device. We expose conversions made from DFG scheduling and mapping with As Soon As Possible (ASAP), As Late As Possible (ALAP) and Random scheduling algorithms. All codes are simulated with Xilinx ISE Design Suite to demonstrate its validity.