I. Introduction
During manufacturing test, the power dissipation of an integrated circuit is much higher than during normal functional mode [1]–[3]. Especially during at-speed scan testing, high Launch-Switching-Activity (LSA) can be a serious problem. LSA is introduced by the transition launch in the initial time frame of the test. Excessive power dissipation in localized High-Capture-Power (HCP) regions is able to induce severe IR-drop during the capture cycle. This may cause a correct circuit under test to fail during testing [4], leading to overtesting and yield loss.