Ultra wide band low noise amplifier with self-bias for improved gain and reduced power dissipation

This paper presents ultra wide band low noise amplifier (LNA) with three stages for 1.9 to 8.2 GHz frequency band based on CMOS technology. In this LNA, first stage is designed on current reuse topology to achieve higher gain, while second stage is complementary push pull configuration in self biased state, which provides high gain and low noise contribution and the third stage is common source stage. This paper proposes two different designs. These designs are optimized for different set of parameters, which makes them suitable for two different categories of applications. The first design with single power source, is able to achieve gain of 21dB with average noise figure of 1.41 dB. Also, 3
^rd
order intercept point (IIP3) and 1-dB compression point are 6 dBm and -17 dBm respectively. While second design achieves reduction in the power dissipation and enhances input output impedance matching. Power dissipation of the second design is 4.1 mW only. Both Ultra Wide Band Low Noise Amplifiers (UWBLNA) are designed and simulated using TMSC 130 nm CMOS technology.