Embedded hybrid LDO topologies for digital load circuits

Digital low dropout voltage regulators provide digital process synthesizability, fast transient response and performance adaptation but lack steady state voltage regulation performance. To overcome this lack of steady state accuracy due to limit cycle oscillations, a hybrid low dropout voltage regulator topology designed in 130 nm CMOS process is presented. In the proposed topology, the operational discrete dynamics of a digital regulator are augmented with continuous dynamics of an analog regulator in a parallel controller configuration to achieve better steady state performance. It has been shown that a higher gain bandwidth product of the analog LDO achieves greater reduction of limit cycle oscillations but uneven controller strengths and power consumption limits its use for wide operational range of digital load circuits.