High speed efficient FPGA implementation of pipelined AES S-Box

Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption Standard (AES) is the most widely and secure symmetric key encryption algorithms today. S-box substitution is the only non-linear step in this algorithm. It is one of the most complicated and costly part of the system. In this article, we present high speed efficient S-box AES architecture using combinational logic. We have used 5-stage pipeline design in order to increase the speed and the maximum operation frequency. Therefore registers are inserted in optimal placements. The implementation has been successfully done by virtex-6 (xc6vlx240t) FPGA device using Xilinx ISE 14.7. Our proposed design achieves a frequency of 842.744 MHz and occupied 20 slices, whereas the highest operation frequency reported in the literature is 696.37 MHz using 32 slices.

I. Introduction

In smart cities, information security plays a major role in protecting the higher levels of confidentiality, availability, and integrity as well as the stability that national services and organizations need to support sustainable and livable smart environments. Cryptographic algorithms are used for security services in various environments in which less number of hardware resources used, high speed and power consumption are key requirements. The Advanced Encryption Standard (AES), also known as Rijndael is an encryption algorithm developed by Dr. Joan Daemen and Dr. Vincent Rijmen [1]. In 2001, it was adopted as a Federal Information Processing Standard by the National Institute of Standards and Technology [2]. S-box substitution is at the core of any AES implementation. It is the only non-linear and complex step in each round of encryption algorithm. There are different implementations of AES S-box, among them, three main. The first, by direct mapping from lookup table (LUT) which stores all predefined 256 8-bit values of S-box in a Read-Only-Memory (ROM) [3], [10], [12]–. The second, using composite field arithmetic in which the field operations are implemented in lower order fields and by lower cost subfield operations [9], [11] and the third by using combinational logic only, to avoid the unbreakable delay of LUTs and to achieve any further increase in processing speed [6]–[8]. In this article, S-box implementation using combinational logic is adopted.